SoC Design

Zero Skipping in AI Accelerators: Architecture, Physical Constraints, and Engineering Trade-offs April 1, 2026 · AI Semiconductors · SoC Design · NPU Architecture In AI accelerator and NPU design, zero skipping is a technique that detects zero values in a data stream and bypasses them entirely — skipping the computation or the transfer. The arithmetic justification is trivially simple: multiplying by zero always yields zero, so those multiply-accumulate (MAC) cycles are wasted work. The engineering challenge, however, is far from trivial. Realizing zero skipping on silicon demands navigating hard physical constraints in area, timing, and routing congestion. This post breaks down the mechanism from first principles through to the practical engineering strategies that make it manufacturable. What Is Zero Skipping? Core Concept Zero skipping detects zero-valued operands in a data stream and eliminates them from computation or transmission. Because x × 0 = 0 for any x , any...

Binary and Gray Code — Designing Signal Reliability Into Silicon SoC Architecture · Arm Cortex-A55 · Digital Design Essentials In digital system design and SoC (System on Chip) architecture, how you represent data is far more than a bookkeeping decision. It directly determines a system's reliability , power efficiency , and timing correctness . This article examines how high-performance processors like the Arm Cortex-A55 (CA55) handle binary counters internally, and why Gray code is not merely an option but a requirement in specific design contexts. Binary Representation in Hardware Decimal vs. Binary: Why Hardware Thinks in Two States The decimal (base-10) system we use daily relies on ten symbols (0–9). Logic gates inside a computer or SoC, however, can only distinguish between two voltage levels — high and low — which maps naturally to a base-2, or binary , number system. Binary is a weighted positional code : each bit position carries a weight of 2ⁿ. For example, ...

🔧 AXI Master Transaction ID Collision Prevention in SoC Interconnects A deep dive into how interconnects transparently resolve AXI ID conflicts in modern chip design 🎯 Why This Problem Matters A modern SoC (System-on-Chip) typically contains dozens of AXI masters — CPUs, GPUs, DMA engines, display controllers, and more — all sharing a common interconnect to reach memory and peripherals. These masters are almost always designed independently by different IP vendors, each assigning their own transaction IDs with no coordination across the system. The possibility of ID overlap is therefore inherent in multi-master SoC design. When IDs collide, responses get routed to the wrong master, ordering guarantees break down, and the system either corrupts data or hangs entirely — a silent, catastrophic hardware bug. This article examines how the AXI protocol and interconnect hardware solve this problem by design, without requiring any coordination between individual master IPs. 📚 A...

Outstanding Transactions in SoC Design: A Deep Dive Latency hiding, pipelined bus throughput, and AMBA AXI architecture In modern SoC design, outstanding transactions are a decisive factor in system performance. By converting physical memory latency into logical parallelism, this technique underpins the performance architecture of every high-throughput chip — from mobile application processors to data center SoCs. What Is an Outstanding Transaction? In SoC interconnect terminology, "outstanding" refers to a master's ability to issue the next transaction before receiving the response to the previous one. The master does not stall; it keeps the address channel busy while data is in flight. Traditional bus protocols such as early AHB used a blocking request-response model : the master sent one request, waited for the completion signal, and only then proceeded. This is analogous to a checkout counter where the next customer cannot place items on the belt unt...