SoC Design

Semiconductor Engineering Roles: A Complete Map from RTL to Fab Equipment Semiconductor engineering spans three stages: Design → Fab (fabrication/manufacturing) → Packaging & Test (OSAT) . Even the same functional role carries different job titles depending on whether you work at a foundry or a fabless company. One particularly notorious trap: the acronym "PI" refers to two completely unrelated disciplines — Power Integrity on the design side, and Process Integration on the fab side. This guide maps every major role across the full semiconductor value chain — front-end and back-end design, IP and DSP engineering, digital and analog IC design, and fab equipment engineering — into a single reference. 📌 Critical disambiguation: In semiconductors, "front-end" and "back-end" mean different things depending on context. ① Manufacturing context: Front-end = wafer processing in the fab; Back-end = dicing, packaging, and testing (OSAT). ② Design cont...

The Golden Rule of SoC Crypto IP Verification — A Complete Golden Reference Guide 📅 May 19, 2026 · 🔐 Cryptographic Algorithms · 🧪 RTL Verification · 🏛️ NIST / XKCP / OpenSSL When embedding crypto IP — AES, SHA-2/3, HMAC/KMAC, RSA — into an SoC, the first question is deceptively simple: "How do you prove this RTL is bit-accurate?" The answer is a verifiable software reference model — a Golden Reference — combined with test vectors sanctioned by a standards body. Passing NIST CAVP vectors is the baseline, not the finish line. In practice, the real debugging leverage comes from a clean C reference that exposes intermediate values at every round. This guide covers: the authoritative standard for each algorithm, the trust hierarchy of golden reference candidates, where to obtain them, required test vector categories, and the critical pitfall of reaching for OpenSSL as a golden model. 🧭 Verification Workflow — The Full Pipeline at a Glance Crypto RTL verification ...

🔐 SHA-3 Crypto Engine Internals: Sponge Construction, SHAKE/cSHAKE/KMAC, and Verilog RTL 📅 May 13, 2026 · Hardware Security · Cryptographic Hardware · PQC Published as FIPS 202 by NIST in 2015, SHA-3 is far more than a next-generation hash function. Built on a single primitive called the Sponge Construction , it serves as the foundation for a multipurpose cryptographic engine capable of handling hashing, XOFs (extendable-output functions), MACs, and KDFs from one core. With all post-quantum cryptography (PQC) standards — ML-KEM, ML-DSA, and SLH-DSA — depending on the SHAKE family, SHA-3 has become essential IP in next-generation secure SoCs. This article covers the full picture: from the mathematical definition of the algorithm through Verilog RTL design trade-offs to side-channel resistance. 1. 🧽 Sponge Construction: Breaking from the Merkle-Damgård Paradigm SHA-1 and SHA-2 both adopted the Merkle-Damgård construction, which is inherently vulnerable to the length-ex...